mmDP1_DP_DPHY_PRBS_CNTL 4549 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmDP1_DP_DPHY_PRBS_CNTL                                                 0x4bb5
mmDP1_DP_DPHY_PRBS_CNTL 4539 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmDP1_DP_DPHY_PRBS_CNTL                                                 0x4bb5
mmDP1_DP_DPHY_PRBS_CNTL 5771 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmDP1_DP_DPHY_PRBS_CNTL                                                 0x4bb5
mmDP1_DP_DPHY_PRBS_CNTL 10522 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP1_DP_DPHY_PRBS_CNTL                                                                        0x1a33
mmDP1_DP_DPHY_PRBS_CNTL 3177 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmDP1_DP_DPHY_PRBS_CNTL 0x1FD4
mmDP1_DP_DPHY_PRBS_CNTL 3917 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmDP1_DP_DPHY_PRBS_CNTL                                                 0x1fd4
mmDP1_DP_DPHY_PRBS_CNTL 8699 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
mmDP1_DP_DPHY_PRBS_CNTL 11310 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
mmDP1_DP_DPHY_PRBS_CNTL 10216 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d