mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 4638 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4bdd
mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 5870 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4bdd
mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 10586 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x1a5b
mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 8759 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 11370 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 10276 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245