mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 10207 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 8358 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 10951 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 9857 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2