mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 10283 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 8430 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 11023 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 9929 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2