mmDP0_DP_SEC_CNTL3_BASE_IDX 8474 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
mmDP0_DP_SEC_CNTL3_BASE_IDX 11067 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
mmDP0_DP_SEC_CNTL3_BASE_IDX 9973 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2