mmDP0_DP_SEC_CNTL1 4644 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmDP0_DP_SEC_CNTL1                                                      0x4ac4
mmDP0_DP_SEC_CNTL1 4677 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmDP0_DP_SEC_CNTL1                                                      0x4ac4
mmDP0_DP_SEC_CNTL1 5909 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmDP0_DP_SEC_CNTL1                                                      0x4ac4
mmDP0_DP_SEC_CNTL1 10262 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP0_DP_SEC_CNTL1                                                                             0x1942
mmDP0_DP_SEC_CNTL1 3151 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmDP0_DP_SEC_CNTL1 0x1CAB
mmDP0_DP_SEC_CNTL1 4012 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmDP0_DP_SEC_CNTL1                                                      0x1cab
mmDP0_DP_SEC_CNTL1 8409 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP0_DP_SEC_CNTL1                                                                             0x212c
mmDP0_DP_SEC_CNTL1 11002 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP0_DP_SEC_CNTL1                                                                             0x212c
mmDP0_DP_SEC_CNTL1 9908 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP0_DP_SEC_CNTL1                                                                             0x212c