mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 10279 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 8426 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 11019 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 9925 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2