mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 8464 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 11057 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 9963 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2