mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 8460 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 11053 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 9959 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2