mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 8458 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 11051 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 9957 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2