mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 10229 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 8380 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 10973 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 9879 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2