mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 10239 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 8390 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 10983 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 9889 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2