mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 10303 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 8450 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 11043 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 9949 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2