mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 4637 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4add
mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 5869 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                      0x4add
mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 10302 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x195b
mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 8449 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 11042 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 9948 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145