mmDMU_MEM_PWR_CNTL_BASE_IDX  931 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDMU_MEM_PWR_CNTL_BASE_IDX                                                                    2
mmDMU_MEM_PWR_CNTL_BASE_IDX  597 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDMU_MEM_PWR_CNTL_BASE_IDX                                                                    2
mmDMU_MEM_PWR_CNTL_BASE_IDX  559 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDMU_MEM_PWR_CNTL_BASE_IDX                                                                    2