mmDMU_MEM_PWR_CNTL  930 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDMU_MEM_PWR_CNTL                                                                             0x00cc
mmDMU_MEM_PWR_CNTL  596 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDMU_MEM_PWR_CNTL                                                                             0x00cc
mmDMU_MEM_PWR_CNTL  558 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDMU_MEM_PWR_CNTL                                                                             0x00cc