mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 1281 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2
mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 1001 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2
mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX  669 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2
mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX  631 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2