mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX  733 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX                                                             1
mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX  933 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX                                                             2
mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX  599 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX                                                             2
mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX  561 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX                                                             2