mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 1273 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2
mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX  991 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2
mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX  659 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2
mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX  621 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2