mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 1271 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2
mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX  987 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2
mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX  655 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2
mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX  617 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2