mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 10471 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 8646 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 11253 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 10159 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2