mmDIG1_TMDS_CNTL 4180 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmDIG1_TMDS_CNTL                                                        0x4b6b
mmDIG1_TMDS_CNTL 4109 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmDIG1_TMDS_CNTL                                                        0x4b6b
mmDIG1_TMDS_CNTL 5340 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmDIG1_TMDS_CNTL                                                        0x4b6b
mmDIG1_TMDS_CNTL 10452 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDIG1_TMDS_CNTL                                                                               0x19e9
mmDIG1_TMDS_CNTL 2637 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmDIG1_TMDS_CNTL 0x1F7C
mmDIG1_TMDS_CNTL 3401 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmDIG1_TMDS_CNTL                                                        0x1f7c
mmDIG1_TMDS_CNTL 8627 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDIG1_TMDS_CNTL                                                                               0x21d3
mmDIG1_TMDS_CNTL 11232 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDIG1_TMDS_CNTL                                                                               0x21d3
mmDIG1_TMDS_CNTL 10138 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDIG1_TMDS_CNTL                                                                               0x21d3