mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 10415 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 8590 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 11195 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 10101 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2