mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 10185 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 8334 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 10923 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 9829 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2