mmDIG0_TMDS_CONTROL_CHAR 4187 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmDIG0_TMDS_CONTROL_CHAR                                                0x4a6c
mmDIG0_TMDS_CONTROL_CHAR 4118 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmDIG0_TMDS_CONTROL_CHAR                                                0x4a6c
mmDIG0_TMDS_CONTROL_CHAR 5349 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmDIG0_TMDS_CONTROL_CHAR                                                0x4a6c
mmDIG0_TMDS_CONTROL_CHAR 10170 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDIG0_TMDS_CONTROL_CHAR                                                                       0x18ea
mmDIG0_TMDS_CONTROL_CHAR 2554 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmDIG0_TMDS_CONTROL_CHAR 0x1C7D
mmDIG0_TMDS_CONTROL_CHAR 3408 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmDIG0_TMDS_CONTROL_CHAR                                                0x1c7d
mmDIG0_TMDS_CONTROL_CHAR 8319 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDIG0_TMDS_CONTROL_CHAR                                                                       0x20d4
mmDIG0_TMDS_CONTROL_CHAR 10906 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDIG0_TMDS_CONTROL_CHAR                                                                       0x20d4
mmDIG0_TMDS_CONTROL_CHAR 9812 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDIG0_TMDS_CONTROL_CHAR                                                                       0x20d4