mmDIG0_TMDS_CNTL 4179 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmDIG0_TMDS_CNTL                                                        0x4a6b
mmDIG0_TMDS_CNTL 4108 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmDIG0_TMDS_CNTL                                                        0x4a6b
mmDIG0_TMDS_CNTL 5339 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmDIG0_TMDS_CNTL                                                        0x4a6b
mmDIG0_TMDS_CNTL 10168 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDIG0_TMDS_CNTL                                                                               0x18e9
mmDIG0_TMDS_CNTL 2552 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmDIG0_TMDS_CNTL 0x1C7C
mmDIG0_TMDS_CNTL 3400 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmDIG0_TMDS_CNTL                                                        0x1c7c
mmDIG0_TMDS_CNTL 8317 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDIG0_TMDS_CNTL                                                                               0x20d3
mmDIG0_TMDS_CNTL 10904 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDIG0_TMDS_CNTL                                                                               0x20d3
mmDIG0_TMDS_CNTL 9810 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDIG0_TMDS_CNTL                                                                               0x20d3