mmDIG0_HDMI_CONTROL_BASE_IDX 10045 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
mmDIG0_HDMI_CONTROL_BASE_IDX 8196 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
mmDIG0_HDMI_CONTROL_BASE_IDX 10781 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
mmDIG0_HDMI_CONTROL_BASE_IDX 9687 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDIG0_HDMI_CONTROL_BASE_IDX                                                                   2