mmDIG0_HDMI_ACR_32_1_BASE_IDX 10119 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
mmDIG0_HDMI_ACR_32_1_BASE_IDX 8268 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
mmDIG0_HDMI_ACR_32_1_BASE_IDX 10855 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
mmDIG0_HDMI_ACR_32_1_BASE_IDX 9761 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2