mmDC_PGCNTL_STATUS_REG   48 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmDC_PGCNTL_STATUS_REG                                                  0x2d5
mmDC_PGCNTL_STATUS_REG   44 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmDC_PGCNTL_STATUS_REG                                                  0x2d5
mmDC_PGCNTL_STATUS_REG   51 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmDC_PGCNTL_STATUS_REG                                                  0x2d5
mmDC_PGCNTL_STATUS_REG  972 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDC_PGCNTL_STATUS_REG                                                                         0x00ad
mmDC_PGCNTL_STATUS_REG 2459 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmDC_PGCNTL_STATUS_REG 0x177E
mmDC_PGCNTL_STATUS_REG   48 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmDC_PGCNTL_STATUS_REG                                                  0x177e
mmDC_PGCNTL_STATUS_REG  898 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDC_PGCNTL_STATUS_REG                                                                         0x00ae