mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX  745 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX  545 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX  189 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX  203 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1