mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 1885 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 1077 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
mmDC_GPU_TIMER_READ_CNTL_BASE_IDX  751 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
mmDC_GPU_TIMER_READ_CNTL_BASE_IDX  713 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2