mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX  893 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX  559 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX  521 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2