mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 1869 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 10412 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 12783 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 11357 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2