mmDCIO_GSL_GENLK_PAD_CNTL 1577 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmDCIO_GSL_GENLK_PAD_CNTL                                               0x4824
mmDCIO_GSL_GENLK_PAD_CNTL 1402 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmDCIO_GSL_GENLK_PAD_CNTL                                               0x4824
mmDCIO_GSL_GENLK_PAD_CNTL 1482 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmDCIO_GSL_GENLK_PAD_CNTL                                               0x4824
mmDCIO_GSL_GENLK_PAD_CNTL 1868 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDCIO_GSL_GENLK_PAD_CNTL                                                                      0x20a2
mmDCIO_GSL_GENLK_PAD_CNTL 1352 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmDCIO_GSL_GENLK_PAD_CNTL 0x1922
mmDCIO_GSL_GENLK_PAD_CNTL 1290 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmDCIO_GSL_GENLK_PAD_CNTL                                               0x1922
mmDCIO_GSL_GENLK_PAD_CNTL 10411 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
mmDCIO_GSL_GENLK_PAD_CNTL 12782 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
mmDCIO_GSL_GENLK_PAD_CNTL 11356 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c