mmDCCG_GTC_CNTL_BASE_IDX  709 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmDCCG_GTC_CNTL_BASE_IDX                                                                       1
mmDCCG_GTC_CNTL_BASE_IDX  517 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmDCCG_GTC_CNTL_BASE_IDX                                                                       1
mmDCCG_GTC_CNTL_BASE_IDX  171 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmDCCG_GTC_CNTL_BASE_IDX                                                                       1
mmDCCG_GTC_CNTL_BASE_IDX  185 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmDCCG_GTC_CNTL_BASE_IDX                                                                       1