mmDAGB1_WR_VC1_CNTL_BASE_IDX  441 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h #define mmDAGB1_WR_VC1_CNTL_BASE_IDX                                                                   0
mmDAGB1_WR_VC1_CNTL_BASE_IDX  441 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h #define mmDAGB1_WR_VC1_CNTL_BASE_IDX                                                                   0
mmDAGB1_WR_VC1_CNTL_BASE_IDX  437 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h #define mmDAGB1_WR_VC1_CNTL_BASE_IDX                                                                   1