mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX  433 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX                                                      0
mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX  433 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX                                                      0
mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX  429 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX                                                      1