mmDAGB0_WR_VC5_CNTL  192 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h #define mmDAGB0_WR_VC5_CNTL                                                                            0x0052
mmDAGB0_WR_VC5_CNTL  216 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h #define mmDAGB0_WR_VC5_CNTL                                                                            0x005e
mmDAGB0_WR_VC5_CNTL  280 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h #define mmDAGB0_WR_VC5_CNTL                                                                            0x007e
mmDAGB0_WR_VC5_CNTL  192 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h #define mmDAGB0_WR_VC5_CNTL                                                                            0x0052
mmDAGB0_WR_VC5_CNTL  192 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h #define mmDAGB0_WR_VC5_CNTL                                                                            0x0052