mmDAGB0_WR_VC4_CNTL  190 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h #define mmDAGB0_WR_VC4_CNTL                                                                            0x0051
mmDAGB0_WR_VC4_CNTL  214 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h #define mmDAGB0_WR_VC4_CNTL                                                                            0x005d
mmDAGB0_WR_VC4_CNTL  278 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h #define mmDAGB0_WR_VC4_CNTL                                                                            0x007d
mmDAGB0_WR_VC4_CNTL  190 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h #define mmDAGB0_WR_VC4_CNTL                                                                            0x0051
mmDAGB0_WR_VC4_CNTL  190 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h #define mmDAGB0_WR_VC4_CNTL                                                                            0x0051