mmDAGB0_WR_VC0_CNTL  182 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h #define mmDAGB0_WR_VC0_CNTL                                                                            0x004d
mmDAGB0_WR_VC0_CNTL  206 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h #define mmDAGB0_WR_VC0_CNTL                                                                            0x0059
mmDAGB0_WR_VC0_CNTL  270 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h #define mmDAGB0_WR_VC0_CNTL                                                                            0x0079
mmDAGB0_WR_VC0_CNTL  182 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h #define mmDAGB0_WR_VC0_CNTL                                                                            0x004d
mmDAGB0_WR_VC0_CNTL  182 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h #define mmDAGB0_WR_VC0_CNTL                                                                            0x004d