mmDAGB0_WR_CNTL_MISC_BASE_IDX  199 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h #define mmDAGB0_WR_CNTL_MISC_BASE_IDX                                                                  0
mmDAGB0_WR_CNTL_MISC_BASE_IDX  223 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h #define mmDAGB0_WR_CNTL_MISC_BASE_IDX                                                                  0
mmDAGB0_WR_CNTL_MISC_BASE_IDX  287 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h #define mmDAGB0_WR_CNTL_MISC_BASE_IDX                                                                  0
mmDAGB0_WR_CNTL_MISC_BASE_IDX  199 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h #define mmDAGB0_WR_CNTL_MISC_BASE_IDX                                                                  0
mmDAGB0_WR_CNTL_MISC_BASE_IDX  199 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h #define mmDAGB0_WR_CNTL_MISC_BASE_IDX                                                                  1