mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX  161 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        0
mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX  177 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        0
mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX  233 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        0
mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX  161 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_3_0_offset.h #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        0
mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX  161 drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1