mmD6VGA_CONTROL_BASE_IDX  647 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmD6VGA_CONTROL_BASE_IDX                                                                       1
mmD6VGA_CONTROL_BASE_IDX  457 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmD6VGA_CONTROL_BASE_IDX                                                                       1
mmD6VGA_CONTROL_BASE_IDX  125 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmD6VGA_CONTROL_BASE_IDX                                                                       1
mmD6VGA_CONTROL_BASE_IDX  145 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmD6VGA_CONTROL_BASE_IDX                                                                       1