mmD5VGA_CONTROL_BASE_IDX  645 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmD5VGA_CONTROL_BASE_IDX                                                                       1
mmD5VGA_CONTROL_BASE_IDX  455 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmD5VGA_CONTROL_BASE_IDX                                                                       1
mmD5VGA_CONTROL_BASE_IDX  123 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmD5VGA_CONTROL_BASE_IDX                                                                       1
mmD5VGA_CONTROL_BASE_IDX  143 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmD5VGA_CONTROL_BASE_IDX                                                                       1