mmD3VGA_CONTROL_BASE_IDX  641 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmD3VGA_CONTROL_BASE_IDX                                                                       1
mmD3VGA_CONTROL_BASE_IDX  451 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmD3VGA_CONTROL_BASE_IDX                                                                       1
mmD3VGA_CONTROL_BASE_IDX  119 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmD3VGA_CONTROL_BASE_IDX                                                                       1
mmD3VGA_CONTROL_BASE_IDX  139 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmD3VGA_CONTROL_BASE_IDX                                                                       1