mmD1VGA_CONTROL_BASE_IDX  575 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmD1VGA_CONTROL_BASE_IDX                                                                       1
mmD1VGA_CONTROL_BASE_IDX  409 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmD1VGA_CONTROL_BASE_IDX                                                                       1
mmD1VGA_CONTROL_BASE_IDX   53 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmD1VGA_CONTROL_BASE_IDX                                                                       1
mmD1VGA_CONTROL_BASE_IDX  113 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmD1VGA_CONTROL_BASE_IDX                                                                       1