mmCRTC0_CRTC_COUNT_RESET  501 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_d.h #define mmCRTC0_CRTC_COUNT_RESET                                                0x1baa
mmCRTC0_CRTC_COUNT_RESET  414 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h #define mmCRTC0_CRTC_COUNT_RESET                                                0x1baa
mmCRTC0_CRTC_COUNT_RESET  421 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_d.h #define mmCRTC0_CRTC_COUNT_RESET                                                0x1baa
mmCRTC0_CRTC_COUNT_RESET 4140 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h #define mmCRTC0_CRTC_COUNT_RESET                                                                       0x06fd
mmCRTC0_CRTC_COUNT_RESET  502 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h #define mmCRTC0_CRTC_COUNT_RESET 0x1BAA
mmCRTC0_CRTC_COUNT_RESET  432 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_d.h #define mmCRTC0_CRTC_COUNT_RESET                                                0x1baa