mmCP_SEM_WAIT_TIMER_BASE_IDX 7197 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_SEM_WAIT_TIMER_BASE_IDX                                                                   1
mmCP_SEM_WAIT_TIMER_BASE_IDX 4699 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_SEM_WAIT_TIMER_BASE_IDX                                                                   1
mmCP_SEM_WAIT_TIMER_BASE_IDX 4951 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_SEM_WAIT_TIMER_BASE_IDX                                                                   1
mmCP_SEM_WAIT_TIMER_BASE_IDX 4907 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_SEM_WAIT_TIMER_BASE_IDX                                                                   1