mmCP_SC_PSINVOC_COUNT0_LO 7078 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_SC_PSINVOC_COUNT0_LO                                                                      0x202c
mmCP_SC_PSINVOC_COUNT0_LO 4596 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_SC_PSINVOC_COUNT0_LO                                                                      0x202c
mmCP_SC_PSINVOC_COUNT0_LO 4848 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_SC_PSINVOC_COUNT0_LO                                                                      0x202c
mmCP_SC_PSINVOC_COUNT0_LO 4804 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_SC_PSINVOC_COUNT0_LO                                                                      0x202c
mmCP_SC_PSINVOC_COUNT0_LO  538 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h #define mmCP_SC_PSINVOC_COUNT0_LO 0x212C
mmCP_SC_PSINVOC_COUNT0_LO  397 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmCP_SC_PSINVOC_COUNT0_LO                                               0xc02c
mmCP_SC_PSINVOC_COUNT0_LO  409 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmCP_SC_PSINVOC_COUNT0_LO                                               0xc02c
mmCP_SC_PSINVOC_COUNT0_LO  445 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmCP_SC_PSINVOC_COUNT0_LO                                               0xc02c
mmCP_SC_PSINVOC_COUNT0_LO  445 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmCP_SC_PSINVOC_COUNT0_LO                                               0xc02c