mmCP_RING2_PRIORITY_BASE_IDX 4749 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_RING2_PRIORITY_BASE_IDX                                                                   0
mmCP_RING2_PRIORITY_BASE_IDX 2384 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_RING2_PRIORITY_BASE_IDX                                                                   0
mmCP_RING2_PRIORITY_BASE_IDX 2683 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_RING2_PRIORITY_BASE_IDX                                                                   0
mmCP_RING2_PRIORITY_BASE_IDX 2621 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_RING2_PRIORITY_BASE_IDX                                                                   0